1. Field of the Invention
The present invention relates to a method of characterizing a semiconductor device and a semiconductor device, and more particularly, to a method of characterizing a floating body silicon-on-insulator (FB SOI) semiconductor device and a semiconductor device used in said method.
2. Description of the Prior Art
With demands for high performance applications, silicon-on-insulator (SOI) technology is developed to provide advantages over conventional bulk metal-oxide-semiconductor field-effect transistor (MOSFET) device that is not able to suppress ultra-short channel effect, and undesired parasitic capacitance and leakage current due to unavoidably PN junctions existed in the bulk silicon MOSFET device.
In SOI technology, the MOSFET device is built on a silicon layer which is separated from a substrate by a buried oxide (BOX) layer. The SOI MOSFET device possesses smaller parasitic capacitance that resulting in superior speed characteristics in circuit operation. The SOI MOSFET device is more radiation-resistant; therefore soft-error immunity is improved. Due to the BOX layer sandwiched between the silicon layer and the substrate, latch-up effect is prevented. Furthermore, since the SOI MOSFET device is not that susceptible to the short channel effect, it is more easily to be scaled down. Based on the benefits of high performance, high packaging density and low power consumption, the SOI MOSFET device is taken as next mainstream device in the future.
According to the thickness of the silicon layer formed on the BOX layer, SOI technology is divided into the partially depleted (PD) SOI and the fully depleted (FD) SOI. And the PD SOI technology is predominant due to higher productivity in the state-of-the-art. Please refer to FIG. 1, which is a schematic diagram of a conventional PD SOI device. The PD SOI device 100 is positioned on a SOI substrate 110, the SOI substrate 110 comprises a substrate 112, a silicon layer 116 and a BOX layer 114 sandwiched between the substrate 112 and the silicon layer 116. The PD SOI device 100 comprises a gate conductive layer 120, a gate dielectric layer 122, and a source/drain 124. The silicon layer 116 of the PD SOI device is thicker than the depletion region, therefore a portion of the SOI substrate 110 is not depleted. Accordingly, a body 126 of the PD SOI device 100 is a floating body. Furthermore, the body 126 of the PD SOI device 100 is not grounded, therefore carriers generated by impact ionization are accumulated. Accordingly, the body potential of the PD SOI device 100 floats in different operation conditions such as in static, dynamic, or transient state, which leads to change of the threshold voltage of the PD SOI device 100, so-called hysteresis effect or history effect. Briefly speaking, the body potential and the characteristics of the PD SOI device 100 are susceptible to the history effect.
As mentioned, since the body 126 of the PD SOI device 100 is not grounded and the characteristics of the PD SOI device 100 is susceptible to the history effect, real characteristics such as the gate-to-body capacitance (Cgb) and the tunneling current (Igb) of the PD SOI device 100, specifically of the floating body (FB) SOI device, are not able to be characterized in the state-of-the-art.
In addition, it is well-known that the input impedance of the radio frequency (RF) MOSFET devices is given by the gate impedance and the gate capacitance, therefore accurate results of measurement of the gate capacitance are critical to RF circuit simulation. It is also well-known that characteristics analysis is very important: a reliable device model is built on the accurate measurement from which real characteristics of the device are able to be extracted. Accordingly, the device characteristics obtained from said results of measurement are the basis of improvement for the device and process designers.